Optimization of CMOS transistors for low power DC-DC converters

This paper presents analytical derivation of optimum width of CMOS transistors to minimize losses in monolithic buck converters. High optimal width of CMOS transistors entails use of tapered inverter chain as gate driver. A novel technique called "width-switching" is presented, which can be easily incorporated along with the inverter chain to maintain maximum efficiency of buck converter over a range of output power levels. Experimental results from a chip containing optimal CMOS transistors for power levels between 50 mW and 200 mW are presented. Challenges in implementing the width-switching scheme, and technologies in which similar schemes can be used, are also discussed.