A damascene platform for controlled ultra-thin nanowire fabrication

被引:15
作者
Guilmain, M. [1 ]
Labbaye, T. [1 ]
Dellenbach, F. [1 ]
Nauenheim, C. [1 ]
Drouin, D. [1 ]
Ecoffey, S. [1 ]
机构
[1] Univ Sherbrooke, Lab Nanotechnol & Nanosyst, CNRS, INSA Lyon,ECL,CPE Lyon,UJF 3IT,UMI LN2 346, Sherbrooke, PQ J1K 0A5, Canada
基金
加拿大自然科学与工程研究理事会;
关键词
ELECTRICAL-RESISTIVITY; ARRAYS; SIZE; MICROSTRUCTURE; DEPENDENCE; DEPOSITION; CHEMISTRY; SENSORS; SCALE; FILMS;
D O I
10.1088/0957-4484/24/24/245305
中图分类号
TB3 [工程材料学];
学科分类号
0805 ; 080502 ;
摘要
This paper presents a damascene process for the fabrication of titanium micro/nanostructures and nanowires with adjustable thickness down to 2 nm. Their depth is precisely controlled by chemical-mechanical planarization together with in-process electrical characterization. The latter, in combination with a model of the titanium resistivity versus thickness, allows control of the metal line depth in the nanometer range. In summary, we have developed a planarization end point detection method for metal nanostructures. In addition, the model adopted covers geometrical influences like oxidation and ageing. The fabricated titanium nanowire test structures have a thickness ranging from 2 to 25 nm and a width ranging between 15 and 230 nm.
引用
收藏
页数:8
相关论文
共 38 条
[1]   Room temperature gas sensor based on metallic nanowires [J].
Atashbar, MZ ;
Singamaneni, S .
SENSORS AND ACTUATORS B-CHEMICAL, 2005, 111 :13-21
[2]   THE THIN-FILM REACTION BETWEEN TI AND THERMALLY GROWN SIO2 [J].
BARBOUR, JC ;
FISCHER, AEMJ ;
VANDERVEEN, JF .
JOURNAL OF APPLIED PHYSICS, 1987, 62 (06) :2582-2584
[3]   TRENDS IN ADVANCED PROCESS TECHNOLOGY - SUBMICROMETER CMOS DEVICE DESIGN AND PROCESS REQUIREMENTS [J].
BROWN, DM ;
GHEZZO, M ;
PIMBLEY, JM .
PROCEEDINGS OF THE IEEE, 1986, 74 (12) :1678-1702
[4]  
Bunshah R F, 1994, MAT SCI PROCESS TECH
[5]   CHEMICAL BONDING AND REACTIONS AT TI/SI AND TI/OXYGEN/SI INTERFACES [J].
BUTZ, R ;
RUBLOFF, GW ;
HO, PS .
JOURNAL OF VACUUM SCIENCE & TECHNOLOGY A-VACUUM SURFACES AND FILMS, 1983, 1 (02) :771-775
[6]   Ultrathin Nanowires - A Materials Chemistry Perspective [J].
Cademartiri, Ludovico ;
Ozin, Geoffrey A. .
ADVANCED MATERIALS, 2009, 21 (09) :1013-1020
[7]   Fabrication of sub-10-nm silicon nanowire arrays by size reduction lithography [J].
Choi, YK ;
Zhu, J ;
Grunes, J ;
Bokor, J ;
Somorjai, GA .
JOURNAL OF PHYSICAL CHEMISTRY B, 2003, 107 (15) :3340-3343
[8]   Wafer-level chip scale packaging: Benefits for integrated passive devices [J].
Clearfield, HM ;
Young, JL ;
Wijeyesekera, SD ;
Logan, EA .
IEEE TRANSACTIONS ON ADVANCED PACKAGING, 2000, 23 (02) :247-251
[9]   CORRELATION OF ELECTRICAL-RESISTIVITY AND GRAIN-SIZE IN SPUTTERED TITANIUM FILMS [J].
DAY, ME ;
DELFINO, M ;
FAIR, JA ;
TSAI, W .
THIN SOLID FILMS, 1995, 254 (1-2) :285-290
[10]  
Devriendt K, 2012, INT C PLAN CMP TECHN