Automated formal verification for VHDL designs

被引：0
|
作者：
Lin, FY
Li, HC
机构：
来源：
COMPUTERS AND THEIR APPLICATIONS - PROCEEDINGS OF THE ISCA 11TH INTERNATIONAL CONFERENCE | 1996年
关键词：
D O I：
暂无
中图分类号：
TP39 [计算机的应用];
学科分类号：
081203 ; 0835 ;
摘要：
We present an approach to employ symbolic model checker (SMV) to model and verify VHDL specifications. This formalism, although mathematically simple, can model most of the properties of the finite transition system, and so play an important role in the study of their semantics. Hardware can be formally verified by describing both the specification and implementation using VHDL and SMV.
引用
收藏
页码：174 / 177
页数：4
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