Performance Comparison Between Bulk and SOI Junctionless Transistors

被引：63
作者：
Han, Ming-Hung [1 ,2 ]
Chang, Chun-Yen [1 ,2 ]
Chen, Hung-Bin [1 ,2 ]
Wu, Jia-Jiun [1 ,2 ]
Cheng, Ya-Chi [3 ]
Wu, Yung-Chun [3 ]
机构：
[1] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 300, Taiwan
[2] Natl Chiao Tung Univ, Inst Elect, Hsinchu 300, Taiwan
[3] Natl Tsing Hua Univ, Dept Engn & Syst Sci, Hsinchu 300, Taiwan
来源：
IEEE ELECTRON DEVICE LETTERS | 2013年 / 34卷 / 02期
关键词：
Fin-shaped field-effect transistor (FinFET); junctionless (JL); 3-D simulation;
D O I：
10.1109/LED.2012.2231395
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The design and characteristics of a junctionless (JL) bulk FinFET were compared with the silicon-on-insulator (SOI) JL nanowire transistor (JNT) using 3-D quantum transport device simulation. The JL bulk FinFET exhibits a favorable ON/OFF current ratio and short-channel characteristics by reducing the effective channel thickness that is caused by the channel/substrate junction. The drain-induced barrier lowering and the subthreshold slope are about 40 mV and 73 mV/dec, respectively, with an ON/OFF current ratio of 10(5) at W = 10 nm. The JL bulk FinFET is less sensitive to the channel thickness than the SOI JNT. Furthermore, the threshold voltage V-th of the JL bulk FinFET can be easily tuned by varying substrate doping concentration N-sub. The modulation range of V-th as N-sub changes from 10(18) to 10(19) cm(-3), which is around 30%.
引用
收藏
页码：169 / 171
页数：3
相关论文
共 15 条
  • [1] Junctionless Nanowire Transistor (JNT): Properties and design guidelines
    Colinge, J. P.
    Kranti, A.
    Yan, R.
    Lee, C. W.
    Ferain, I.
    Yu, R.
    Akhavan, N. Dehdashti
    Razavi, P.
    [J]. SOLID-STATE ELECTRONICS, 2011, 65-66 : 33 - 37
  • [2] Colinge JP, 2010, NAT NANOTECHNOL, V5, P225, DOI [10.1038/nnano.2010.15, 10.1038/NNANO.2010.15]
  • [3] Reduced electric field in junctionless transistors
    Colinge, Jean-Pierre
    Lee, Chi-Woo
    Ferain, Isabelle
    Akhavan, Nima Dehdashti
    Yan, Ran
    Razavi, Pedram
    Yu, Ran
    Nazarov, Alexei N.
    Doriac, Rodrigo T.
    [J]. APPLIED PHYSICS LETTERS, 2010, 96 (07)
  • [4] Dadgour H., 2008, International Conference on Computer-Aided Design, P1, DOI [10.1109/IEDM.2008.4796792, DOI 10.1109/IEDM.2008.4796792]
  • [5] Mobility and screening effect in heavily doped accumulation-mode metal-oxide-semiconductor field-effect transistors
    Goto, Ken-Ichi
    Yu, Tsung-Hsing
    Wu, Jeff
    Diaz, Carlos H.
    Colinge, J. P.
    [J]. APPLIED PHYSICS LETTERS, 2012, 101 (07)
  • [6] Hisamoto D, 2000, IEEE T ELECTRON DEV, V47, P2320, DOI 10.1109/16.887014
  • [7] Hu CM, 2004, 2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, P4
  • [8] Junctionless multigate field-effect transistor
    Lee, Chi-Woo
    Afzalian, Aryan
    Akhavan, Nima Dehdashti
    Yan, Ran
    Ferain, Isabelle
    Colinge, Jean-Pierre
    [J]. APPLIED PHYSICS LETTERS, 2009, 94 (05)
  • [9] Process-Variation Effect, Metal-Gate Work-Function Fluctuation, and Random-Dopant Fluctuation in Emerging CMOS Technologies
    Li, Yiming
    Hwang, Chih-Hong
    Li, Tien-Yeh
    Han, Ming-Hung
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2010, 57 (02) : 437 - 447
  • [10] Characteristics of n-Type Junctionless Poly-Si Thin-Film Transistors With an Ultrathin Channel
    Lin, Horng-Chih
    Lin, Cheng-I
    Huang, Tiao-Yuan
    [J]. IEEE ELECTRON DEVICE LETTERS, 2012, 33 (01) : 53 - 55
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