S-RCAT (Sphere-shaped-Recess-Channel-Array Transistor) Technology for 70nm DRAM feature size and beyond

被引：0

作者：

Kim, JY ^{[1
]}

Oh, HJ ^{[1
]}

Woo, DS ^{[1
]}

Lee, YS ^{[1
]}

Kim, DH ^{[1
]}

Kim, SE ^{[1
]}

Ha, GW ^{[1
]}

Kim, HJ ^{[1
]}

Kang, NJ ^{[1
]}

Park, JM ^{[1
]}

Hwang, YS ^{[1
]}

Kim, DJ ^{[1
]}

Park, BJ ^{[1
]}

Huh, M ^{[1
]}

Lee, BH ^{[1
]}

Kim, SB ^{[1
]}

Cho, MH ^{[1
]}

Jung, MY ^{[1
]}

Kim, YI ^{[1
]}

Jin, C ^{[1
]}

Shin, DW ^{[1
]}

Shim, MS ^{[1
]}

Lee, CS ^{[1
]}

Lee, WS ^{[1
]}

Park, JC ^{[1
]}

Jin, GY ^{[1
]}

Park, YJ ^{[1
]}

Kim, K ^{[1
]}

机构：

[1] Samsung Elect Co, Adv Technol Dev Semicond R&D Div, Yongin 449711, Kyunggi Do, South Korea

来源：

2005 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2005年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

For the first time, S-RCAT (Sphere-shaped-Recess-Channel-Array Transistor) technology has been successfully developed in a 2Gb density DRAM with 70nm feature size. It is a modified structure of the RCAT (Recess-Charmel-Array Transistor) and shows an excellent scalability of recessed-chamet structure to sub-50nm feature size. The S-RCAT demonstrated superior characteristics in DIBL, subthreshold swing (SR), body effects junction leakage current and data retention time, comparing to the RCAT structure. In this paper, S-RCAT is proved to be the most promising DRAM array transistor suitable for sub-50nm and mobile applications.

引用

页码：34 / 35

页数：2

共 4 条

[1] The excellent scalability of the RCAT(Recess-Channel-Array-Transistor) technology for sub-70nm DRAM feature size and beyond
Kim, JY
Woo, DS
Oh, HJ
Kim, HJ
Kim, SE
Park, BJ
Kwon, JM
Shim, MS
Ha, GW
Song, JW
Kang, NJ
Park, JM
Hwang, HK
Song, SS
Hwang, YS
Kim, DI
Kim, DH
Huh, M
Han, DH
Lee, CS
Park, SJ
Kim, YR
Kim, HJ
Lee, YS
Jung, MY
Kim, YI
Lee, BH
Cho, MH
Choi, WT
Kim, HS
Jin, GY
Park, YJ
Kim, K
2005 IEEE VLSI-TSA International Symposium on VLSI Technology (VLSI-TSA-TECH), Proceedings of Technical Papers, 2005, : 33 - 34
[2] Implementation of HfSiON gate dielectric for sub-60nm DRAM dual gate oxide with recess channel array transistor(RCAT) and tungsten gate
Park, SG
Jin, BJ
Lee, HL
Park, HB
Jeon, TS
Cho, HJ
Kim, SY
Jang, SI
Kang, SB
Shin, YG
Chung, UI
Moon, JT
IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, : 515 - 518
[3] High-density low-power-operating DRAM device adopting 6F2 cell scheme with novel S-RCAT structure on 80nm feature size and beyond
Oh, HJ
Kim, JY
Kim, JH
Park, SG
Kim, DH
Kim, SE
Woo, DS
Lee, YS
Ha, GW
Park, JM
Kang, NJ
Kim, HJ
Hwang, YS
Kim, BY
Kim, DI
Cho, YS
Choi, JK
Lee, BH
Kim, SB
Cho, MH
Kim, YI
Choi, J
Shin, DW
Shim, MS
Choi, WT
Lee, GP
Park, YJ
Lee, WS
Ryu, BI
PROCEEDINGS OF ESSDERC 2005: 35TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2005, : 177 - 180
[4] Improvement of data retention time in DRAM using Recessed Channel Array Transister with Asymmetric Channel doping for 80 nm feature size and beyond
Lee, JW
Kim, YS
Kim, JY
Park, YK
Shin, SH
Lee, SH
Oh, JH
Lee, JG
Lee, JY
Bae, DI
Lee, EC
Lee, CS
Yun, CJ
Cho, CH
Jin, KY
Park, YJ
Chung, TY
Kim, K
ESSDERC 2004: PROCEEDINGS OF THE 34TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2004, : 449 - 452

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