Design of q-Parallel LFSR-Based Syndrome Generator

被引：0

作者：

Kim, Seung-Youl ^{[1
]}

Cho, Kyoung-Rok ^{[1
]}

Lee, Je-Hoon ^{[2
]}

机构：

[1] Chungbuk Natl Univ, Dept Comp & Commun Engn, Cheongju, Chungbuk 361763, South Korea

[2] Kangwon Natl Univ, Div Elect Informat & Commun Engn, Gangwon 245711, South Korea

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 2015年 / E98C卷 / 07期

基金：

新加坡国家研究基金会;

关键词：

error control code; parallel architecture; LFSR; BCH;

D O I：

10.1587/transele.E98.C.594

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a new parallel architecture of syndrome generator for a high-speed BCH (Bose-Chaudhuri-Hocquenghem) decoder. In particular, the proposed parallel syndrome generators are based on LFSR (linear feedback shift register) architecture to achieve high throughput without significant area overhead. From the experimental results, the proposed approach achieves 4.60 Gbps using 0.25-mu m standard CMOS technology. This result is much faster than the conventional byte-wise GFM-based counterpart. The high throughputs are due to the well-tuned hardware implementation using unfolding transformation.

引用

页码：594 / 596

页数：3

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