MOS device conductance modelling technique for an accurate and efficient mixed-mode simulation of CMOS circuits

被引：0
|
作者：
Samudra, G
Lee, TK
机构：
[1] National University of Singapore, Department of Electrical Engineering, Singapore 0511
来源：
ELECTRONICS LETTERS | 1996年 / 32卷 / 03期
关键词：
semiconductor device models; CMOS integrated circuits;
D O I：
10.1049/el:19960103
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A new technique for modelling the conductance of an MOS device for the electrical logic simulation (the Elogic algorithm) of CMOS circuits is proposed. The technique is general and applicable to any analytic device current model. The Elogic algorithm allows the representation of a logic transition using a finite number of voltage steps and calculates time for each transition between the adjacent voltage steps. The examples show that the new technique can correctly predict a complete electrical waveform with a large voltage step of 1V to yield at least an order of magnitude computational time advantage over the circuit simulation.
引用
收藏
页码：264 / 265
页数：2
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