Temporal Performance Degradation under RTN: Evaluation and Mitigation for Nanoscale Circuits

被引：7

作者：

Luo, Hong ^{[1
]}

Wang, Yu ^{[1
]}

Cao, Yu ^{[2
]}

Xie, Yuan ^{[3
]}

Ma, Yuchun

Yang, Huazhong ^{[1
]}

机构：

[1] Tsinghua Univ, Dept EE, TNList, Beijing 100084, Peoples R China

[2] Arizona State Univ, Dept ECEE, Tempe, AZ 85287 USA

[3] Penn State Univ, Dept CSE, University Pk, PA 16802 USA

来源：

2012 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI) | 2012年

基金：

中国国家自然科学基金;

关键词：

Random telegraph noise; Performance degradation; Mitigation technique; RANDOM TELEGRAPH NOISE; SIMULATION; MOSFETS;

D O I：

10.1109/ISVLSI.2012.35

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Random telegraph noise (RTN) is one of the critical reliability concerns in nanoscale circuit design, and it is important to consider the impact of RTN on the circuits' temporal performance. This paper proposes a framework to evaluate the RTN-induced performance degradation and variation of digital circuits, and the evaluation results show that RTN can result in 54.4% degradation and 59.9% variation on the circuit delay at 16nm technology node. Power supply tuning and gate sizing techniques are investigated to demonstrate the impact of such circuit-level techniques on mitigating the RTN effect.

引用

页码：183 / 188

页数：6

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