EFFICIENT HARDWARE ARCHITECTURE FOR LARGE DISPARITY RANGE STEREO MATCHING BASED ON BELIEF PROPAGATION

被引:7
作者
Wu, Sih-Sian [1 ]
Tsai, Chen-Han [1 ]
Chen, Bang-Gee [1 ]
机构
[1] Natl Taipei Univ, DSP IC Design Lab, New Taipei 23741, Taiwan
来源
2016 IEEE INTERNATIONAL WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS) | 2016年
关键词
BP-M; tile-based BP; Hardware implementation; stereo matching; disparity estimation; ENERGY MINIMIZATION; TREE;
D O I
10.1109/SiPS.2016.49
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper introduces an efficient hardware architecture for the belief propagation(BP) algorithm especially for large disparity range stereo matching applications. BP is a popular global optimization algorithm for labelling problems which is hardware friendly. There are few researches focus on BP implementation in large disparity range stereo matching problems, since traditional belief propagation hardware implementations suffer from a server trade-off between hardware efficiency and short critical path while the disparity range is larger than 64. In this paper, we eliminate the redundancy of previous BP implementation and propose an efficient architecture without introducing any delay overhead which is more suitable for large disparity range cases. As a result, the hardware complexity is reduced from O(L-2) to O(Llog(2) L), where L is the disparity range. We use a time-area term to demonstrate the trade-off between various architectures, results show that the proposed one can reach 49.6% and 71.2% reduction compared to the state-of-the-art implementation[1] with disparity ranges 64 and 128 respectively.
引用
收藏
页码:236 / 241
页数:6
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