Adaptive Clock Distribution for 3D Integrated Circuits

被引：0

作者：

Chen, Xi ^{[1
]}

Davis, W. Rhett ^{[1
]}

Franzon, Paul D. ^{[1
]}

机构：

[1] N Carolina State Univ, Dept Elect & Comp Engn, Raleigh, NC 27695 USA

来源：

2011 IEEE 20TH CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS (EPEPS) | 2011年

关键词：

3D IC; clock districution; adaptive; de-skew; GENERATION;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Clock distribution in three-dimensional integrated circuits (3D ICs) is faced with many challenges. In this work, we present new techniques for realizing highly adaptive and reliable clock distribution for 3D ICs. Firstly, an efficient clock distribution topology without need of balanced H-tree is proposed. Secondly, a robust tunable-delay-buffer (TDB) circuit and a novel active de-skew method are developed in order to handle the cross-die variations, thermal gradients, and wiring asymmetry. Moreover, a design optimization flow is constructed for improving the adaptive clock design based on the thermal profiles. Experiment results show that the clock skews are significantly reduced using the proposed techniques.

引用

页码：91 / 94

页数：4

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