Silicon nanowire NVM cell using high-k dielectric charge storage layer

Si nanowire (SiNW) channel non-volatile memory (NVM) cells were fabricated by a "self-alignment" Process. First, a layer of thermal SiO2 was grown on a silicon wafer by dry oxidation, and the SiNWs were then grown by chemical vapor deposition in pre-defined locations. This was followed by depositing the gate dielectric, which almost surrounds the nanowire and consists of three stacked layers: SiO2 blocking layer, HfO2 charge-storing layer and a thin tunneling oxide layer. Source/drain and gate electrodes were formed by photolithography and lift-off, and the devices were electrically tested. As expected from this fabrication process and the enhanced electrostatic control of the "surrounding" gate, excellent cell characteristics were obtained. (C) 2008 Elsevier B.V. All rights reserved.