Low-power design for embedded processors

被引：26

作者：

Moyer, B ^{[1
]}

机构：

[1] Motorola Inc, Austin, TX 78729 USA

来源：

PROCEEDINGS OF THE IEEE | 2001年 / 89卷 / 11期

关键词：

circuit design; clock distribution; clock gating; CMOS circuits; CPU microarchitecture; instruction set design; low-power architecture; low-power design; low-power synthesis; low-power systems; power dissipation; power minimization; power optimization; RISC; state assignment; system design;

D O I：

10.1109/5.964439

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Minimization of power consumption in portable and battery-powered embedded systems has become an important aspect of processor and system design. Opportunities for power optimization and tradeoffs emphasizing low power are available across the entire design hierarchy. A review of low-power techniques applied at many levels of the design hierarchy is presented, and an example of low-power processor architecture is described along with some of the design decisions made in implementation of the architecture.

引用

页码：1576 / 1587

页数：12

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