System-on-a-chip (SoC)-based Hardware Acceleration for Extreme Learning Machine

被引:0
|
作者
Safaei, Amin [1 ]
Wu, Q. M. Jonathan [1 ]
Yang, Yimin [1 ]
Akilan, Thangarajah [1 ]
机构
[1] Univ Windsor, Dept Elect & Comp Engn, Windsor, ON, Canada
基金
加拿大自然科学与工程研究理事会;
关键词
Extreme learning machine; system on chip field-programmable gate array (SoC FPGA); hardware (HW) neural networks (NNs);
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Extreme learning machine (ELM) is a popular class of supervised models in machine learning that is used in a wide range of applications, such as image object classification, video content analysis (VCA) and human action recognition. However, ELM classification is a computationally demanding task, and the existing hardware implementations are not efficient for embedded systems. This work addresses the implementation of extreme learning machine (ELM) in a system on a chip field-programmable gate-array (SoC FPGA)-based customized architecture to efficiently utilize hardware accelerator. The optimization process consists of parallelism extraction, algorithm tuning and deep pipelining.
引用
收藏
页码:470 / 473
页数:4
相关论文
共 50 条
  • [41] Design space exploration methodology for high-performance system-on-a-chip hardware cores
    Sllame, AM
    3RD IEEE INTERNATIONAL WORKSHOP ON SYSTEM-ON-CHIP FOR REAL-TIME APPLICATIONS, PROCEEDINGS, 2003, : 216 - 221
  • [42] An Extreme Learning Machine Based on Artificial Immune System
    Tian, Hui-yuan
    Li, Shi-jian
    Wu, Tian-qi
    Yao, Min
    COMPUTATIONAL INTELLIGENCE AND NEUROSCIENCE, 2018, 2018
  • [43] An Innovative Power-Gating Technique for Leakage and Ground Bounce Control in System-on-a-Chip (SOC)
    Masud H. Chowdhury
    Pervez Khaled
    Juliana Gjanci
    Circuits, Systems, and Signal Processing, 2011, 30 : 89 - 105
  • [44] Hardware support for real-time embedded multiprocessor system-on-a-chip memory management
    Shalan, M
    Mooney, VJ
    CODES 2002: PROCEEDINGS OF THE TENTH INTERNATIONAL SYMPOSIUM ON HARDWARE/SOFTWARE CODESIGN, 2002, : 79 - 84
  • [45] An Innovative Power-Gating Technique for Leakage and Ground Bounce Control in System-on-a-Chip (SOC)
    Chowdhury, Masud H.
    Khaled, Pervez
    Gjanci, Juliana
    CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2011, 30 (01) : 89 - 105
  • [46] Domain Specific Architectures, Hardware Acceleration for Machine/Deep Learning
    Solis, Angel, I
    Nava, Patricia
    DISRUPTIVE TECHNOLOGIES IN INFORMATION SCIENCES II, 2019, 11013
  • [47] Hardware Acceleration on Gaussian Naive Bayes Machine Learning Algorithm
    Tzanos, Georgios
    Kachris, Christoforos
    Soudris, Dimitrios
    2019 8TH INTERNATIONAL CONFERENCE ON MODERN CIRCUITS AND SYSTEMS TECHNOLOGIES (MOCAST), 2019,
  • [48] Hardware Acceleration for DBMS Machine Learning Scoring: Is It Worth the Overheads?
    Azad, Zahra
    Sen, Rathijit
    Park, Kwanghyun
    Joshi, Ajay
    2021 IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE (ISPASS 2021), 2021, : 243 - 253
  • [49] A Hardware Design and Implementation or Accelerating Motion Detection using (System On Chip) SOC
    Khalil, Ahmed S.
    Shalaby, Mohamed
    Hegazi, Emad
    2017 12TH INTERNATIONAL CONFERENCE ON COMPUTER ENGINEERING AND SYSTEMS (ICCES), 2017, : 411 - 416
  • [50] RETRACTED: A pipelined multiprocessor system-on-a-chip (SoC) design methodology for streaming signal processing (Retracted Article)
    Chen, Ching-Han
    Yao, Tun-Kai
    Dai, Jia-Hong
    Chen, Chen-Yuan
    JOURNAL OF VIBRATION AND CONTROL, 2014, 20 (02) : 163 - 178