A 10-bit 150MS/s SAR ADC with a Novel Capacitor Switching Scheme

被引：0

作者：

Mei, Fengyi ^{[1
]}

Shu, Yujun ^{[1
]}

Yu, Youling ^{[1
]}

机构：

[1] Tong Univ, Sch Elect & Informat Engn, Shanghai, Peoples R China

来源：

2017 3RD IEEE INTERNATIONAL CONFERENCE ON COMPUTATIONAL INTELLIGENCE & COMMUNICATION TECHNOLOGY (CICT) | 2017年

关键词：

Capacitor switching scheme; MCS scheme; split CDAC; SAR ADC;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

This paper presents a 10-bit 150-MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC). Firstly, combining the merged capacitor switching scheme (MCS scheme) with the split capacitive digital-to-analog converter (split CDAC), a novel capacitor switching scheme is presented which greatly improve the power efficiency of the ADC. Moreover, the use of a non-binary redundancy algorithm corrects the incomplete settling of the CDAC and increases the sample rate of the ADC. The ADC achieves an SNDR of 51.5 dB for a 15 MHz input and 49.6 dB for a 74.5 MHz input, and the total power consumption is 537 mu W from a 1.2-V supply.

引用

页数：6

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