The FE-I4 pixel readout system-on-chip resubmission for the insertable B-Layer project

被引：20

作者：

Zivkovic, V. ^{[1
]}

Schipper, J-D. ^{[1
]}

Garcia-Sciveres, M. ^{[2
]}

Mekkaoui, A. ^{[2
]}

Barbero, M. ^{[3
]}

Darbo, G. ^{[4
]}

Gnani, D. ^{[2
]}

Hemperek, T. ^{[3
]}

Menouni, M. ^{[5
]}

Fougeron, D. ^{[5
]}

Gensolen, F. ^{[5
]}

Jensen, F. ^{[2
]}

Caminada, L. ^{[2
]}

Gromov, V. ^{[1
]}

Kluit, R. ^{[1
]}

Fleury, J. ^{[6
]}

Krueger, H. ^{[3
]}

Backhaus, M. ^{[3
]}

Fang, X. ^{[3
]}

Gonella, L. ^{[3
]}

Rozanov, A. ^{[5
]}

Arutinov, D. ^{[3
]}

机构：

[1] Natl Inst Subatomaire Fys, Amsterdam, Netherlands

[2] Univ Calif Berkeley, Lawrence Berkeley Natl Lab, Berkeley, CA 94720 USA

[3] Univ Bonn, Bonn, Germany

[4] Inst Nazl Fis Nucl, Sez Genova, Genoa, Italy

[5] Ctr Phys Particules Marseille, Marseille, France

[6] Lab Accelerateur Lineaire, F-91405 Orsay, France

来源：

JOURNAL OF INSTRUMENTATION | 2012年 / 7卷

关键词：

VLSI circuits; Electronic detector readout concepts (solid-state); Digital electronic circuits;

D O I：

10.1088/1748-0221/7/02/C02050

中图分类号：

TH7 [仪器、仪表];

学科分类号：

0804 ; 080401 ; 081102 ;

摘要：

The FE-I4 is a new pixel readout integrated circuit designed to meet the requirements of ATLAS experiment upgrades. The first samples of the FE-I4 engineering run (called FE-I4A) delivered promising results in terms of the requested performances. The FE-I4 team envisaged a number of modifications and fine-tuning before the actual exploitation, planned within the Insertable B-Layer (IBL) of ATLAS. As the IBL schedule was pushed significantly forward, a quick and efficient plan had to be devised for the FE-I4 redesign. This article will present the main objectives of the resubmission, together with the major changes that were a driving factor for this redesign. In addition, the top-level verification and test efforts of the FE-I4 will also be addressed.

引用

页数：7