A 2.4 GHz 0.1-Fref-Bandwidth All-Digital Phase-Locked Loop With Delay-Cell-Less TDC

被引：19

作者：

Song, Minyoung ^{[1
,2
]}

Jung, Inhwa ^{[1
,2
]}

Pamarti, Sudhakar ^{[2
,3
]}

Kim, Chulwoo ^{[1
,2
]}

机构：

[1] Korea Univ, Sch Elect Engn, Seoul 136701, South Korea

[2] Korea Univ, Dept Elect Engn, Seoul 136701, South Korea

[3] Univ Calif Los Angeles, Dept Elect Engn, Los Angeles, CA 90095 USA

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2013年 / 60卷 / 12期

关键词：

All-digital PLL (ADPLL); delay-cell-less TDC; low noise VCO; phase-locked loop (PLL); time-to-digital converter (TDC); RING OSCILLATOR; LOW-NOISE; CONVERTER; PLL;

D O I：

10.1109/TCSI.2013.2265975

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An all-digital phase locked loop (ADPLL) with a proposed time-to-digital converter (TDC) which has no delay cell is designed by the 0.13-mu m CMOS process. The delay-cell-less TDC (DLTDC) that can suppress device noises and PVT mismatches is essential for wider bandwidth operations. Moreover, sub-gate TDC resolution can be achieved with the proposed DLTDC. A ring-VCO based digitally-controlled oscillator (DCO) which reduces 1/f noise is also proposed to enhance noise performance. The 2 MHz BW ADPLL which occupies 0.42 mm(2) consumes 12 mA and its measured jitter is 4 ps(rms) at 2.4 GHz.

引用

页码：3145 / 3151

页数：7

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