Speed superiority of scaled double-gate CMOS

被引：61
作者：
Fossum, JG [1 ]
Ge, LX
Chiang, MH
机构：
[1] Univ Florida, Dept Elect & Comp Engn, Gainesville, FL 32611 USA
[2] Adv Micro Devices Inc, Sunnyvale, CA 94088 USA
来源：
IEEE TRANSACTIONS ON ELECTRON DEVICES | 2002年 / 49卷 / 05期
关键词：
CMOS modeling; double-gate MOSFETs; gate capacitance; propagation delay; on-state current;
D O I：
10.1109/16.998588
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Unloaded ring-oscillator simulations, done with a generic process/physics- based compact model for double-gate (DG) MOSFETs and supplemented with model-predicted on-state currents and gate capacitances for varying supply voltages (V-DD), are used to show and explain the speed superiority of extremely scaled DG CMOS over the single-gate (e.g., bulk-Si) counterpart. The DG superiority for unloaded circuits is most substantive for low VDD < similar to1 V.
引用
收藏
页码：808 / 811
页数：4
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