Low Power & High Performance Implementation of Multiplier Architectures

被引：0

作者：

Verma, Gaurav ^{[1
]}

Shekhar, Sushant ^{[1
]}

Srivastava, Oorja M. ^{[1
]}

Maheshwari, Shikhar ^{[1
]}

Virdi, Sukhbani Kaur ^{[1
]}

机构：

[1] Jaypee Inst Informat Technol, Dept Elect & Commun Engn, A-10,Sect 62, Noida 201307, Uttar Pradesh, India

来源：

PROCEEDINGS OF THE 10TH INDIACOM - 2016 3RD INTERNATIONAL CONFERENCE ON COMPUTING FOR SUSTAINABLE GLOBAL DEVELOPMENT | 2016年

关键词：

Low power; FPGA; CSA; Bypassing Technique;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

In this work, a new technique known as bypass technique has been introduced mainly to reduce the switching power dissipation. In array multipliers, this technique offers huge dynamic power saving but due to their regular interconnection scheme, it misses the reduced area and high speed advantages of tree multipliers. Hence we have introduced a mixed architecture style which contains a tree multiplier and a carry save multiplier with bypass technique ensures high performance also. The implementation has been carried out on Virtex4 FPGA. The power values are obtained from Xpower Analyzer and the results shows the significant reduction in power when tested at different frequencies.

引用

页码：1989 / 1992

页数：4