RTL level trace signal selection and coverage estimation during post-silicon validation

被引:0
作者
Kumar, Binod [1 ]
Basu, Kanad [2 ]
Fujita, Masahiro [3 ]
Singh, Virendra [1 ]
机构
[1] Indian Inst Technol, Bombay, Maharashtra, India
[2] NYU, New York, NY 10003 USA
[3] Univ Tokyo, Tokyo, Japan
来源
2017 IEEE INTERNATIONAL HIGH LEVEL DESIGN VALIDATION AND TEST WORKSHOP (HLDVT) | 2017年
关键词
RTL signal selection; Restorability; Post-silicon validation; Design bugs; Assertions;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Trace buffers play a crucial role in curbing the obstacle of limited observability of internal states for error localization during post-silicon stage. Given the constraint of area over-head, selecting appropriate signals which are to be stored in the trace buffers is of paramount importance for the overall success of this observability enhancement mechanism. This paper proposes a register-transfer level trace signal selection methodology which uses assertions generated during pre-silicon design verification. The enlarged quantity of restored signal states in conjunction with the traced states help to estimate the coverage of particular events during post-silicon validation; thus, acting as a suitable alternative to synthesizing coverage monitors. Experimental results on opencore benchmark circuits indicate that the proposed methodology performs better than existing trace signal selection techniques, which focus on maximization of restoration of untraced signals from the traced ones.
引用
收藏
页码:59 / 66
页数:8
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