PNPN tunnel FET with controllable drain side tunnel barrier width: Proposal and analysis

被引：31

作者：

Abdi, Dawit Burusie ^{[1
]}

Kumar, M. Jagadesh ^{[1
]}

机构：

[1] Indian Inst Technol, Dept Elect Engn, New Delhi 110016, India

来源：

SUPERLATTICES AND MICROSTRUCTURES | 2015年 / 86卷

关键词：

Source-pocket (PNPN) TFET; Tunneling; Pocket implantation; In-built N+ pocket; Charge plasma; Electrostatic doping; 2D TCAD simulation; FIELD-EFFECT TRANSISTORS; RECRYSTALLIZED POLYCRYSTALLINE SILICON; CHARGE-PLASMA TRANSISTOR; DESIGN;

D O I：

10.1016/j.spmi.2015.07.045

中图分类号：

O469 [凝聚态物理学];

学科分类号：

070205 ;

摘要：

A detailed study of a technique to realize a PNPN tunnel field effect transistor (TFET) with a controllable tunnel barrier width on the drain side is reported in this paper. By using the charge plasma concept on a doped N+/P- starting structure, we have demonstrated the possibility of realizing the PNPN TFET without the need for any additional chemically doped junctions. We have showed that using electrostatic doping on the drain side of TFETs provides a new design parameter, the gate-drain electrode gap. This gate-drain electrode gap can be used to control the ambipolar current in TFETs by controlling the tunneling barrier width at the channel-drain junction. (C) 2015 Elsevier Ltd. All rights reserved.

引用

页码：121 / 125

页数：5