PNPN tunnel FET with controllable drain side tunnel barrier width: Proposal and analysis

被引:31
作者
Abdi, Dawit Burusie [1 ]
Kumar, M. Jagadesh [1 ]
机构
[1] Indian Inst Technol, Dept Elect Engn, New Delhi 110016, India
关键词
Source-pocket (PNPN) TFET; Tunneling; Pocket implantation; In-built N+ pocket; Charge plasma; Electrostatic doping; 2D TCAD simulation; FIELD-EFFECT TRANSISTORS; RECRYSTALLIZED POLYCRYSTALLINE SILICON; CHARGE-PLASMA TRANSISTOR; DESIGN;
D O I
10.1016/j.spmi.2015.07.045
中图分类号
O469 [凝聚态物理学];
学科分类号
070205 ;
摘要
A detailed study of a technique to realize a PNPN tunnel field effect transistor (TFET) with a controllable tunnel barrier width on the drain side is reported in this paper. By using the charge plasma concept on a doped N+/P- starting structure, we have demonstrated the possibility of realizing the PNPN TFET without the need for any additional chemically doped junctions. We have showed that using electrostatic doping on the drain side of TFETs provides a new design parameter, the gate-drain electrode gap. This gate-drain electrode gap can be used to control the ambipolar current in TFETs by controlling the tunneling barrier width at the channel-drain junction. (C) 2015 Elsevier Ltd. All rights reserved.
引用
收藏
页码:121 / 125
页数:5
相关论文
共 32 条
[1]   Controlling Ambipolar Current in Tunneling FETs Using Overlapping Gate-on-Drain [J].
Abdi, Dawit B. ;
Kumar, M. Jagadesh .
IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2014, 2 (06) :187-190
[2]   In-Built N+ Pocket p-n-p-n Tunnel Field-Effect Transistor [J].
Abdi, Dawit Burusie ;
Kumar, Mamidala Jagadesh .
IEEE ELECTRON DEVICE LETTERS, 2014, 35 (12) :1170-1172
[3]  
[Anonymous], 2014, ATLAS DEV SIM SOFTW
[4]   Double-gate tunnel FET with high-κ gate dielectric [J].
Boucart, Kathy ;
Mihai Ionescu, Adrian .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (07) :1725-1733
[5]   Improvement in Reliability of Tunneling Field-Effect Transistor With p-n-i-n Structure [J].
Cao, Wei ;
Yao, C. J. ;
Jiao, G. F. ;
Huang, Daming ;
Yu, H. Y. ;
Li, Ming-Fu .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2011, 58 (07) :2122-2126
[6]   Improved Subthreshold and Output Characteristics of Source-Pocket Si Tunnel FET by the Application of Laser Annealing [J].
Chang, Hsu-Yu ;
Adams, Bruce ;
Chien, Po-Yen ;
Li, Jiping ;
Woo, Jason C. S. .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2013, 60 (01) :92-96
[7]   Design optimization of tunneling field-effect transistor based on silicon nanowire PNPN structure and its radio frequency characteristics [J].
Cho, Seongjae ;
Kang, In Man .
CURRENT APPLIED PHYSICS, 2012, 12 (03) :673-677
[8]   Hetero-Gate-Dielectric Tunneling Field-Effect Transistors [J].
Choi, Woo Young ;
Lee, Woojun .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2010, 57 (09) :2317-2319
[9]   Strain-Induced Performance Improvements in InAs Nanowire Tunnel FETs [J].
Conzatti, F. ;
Pala, M. G. ;
Esseni, D. ;
Bano, E. ;
Selmi, L. .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2012, 59 (08) :2085-2092
[10]   Heteromaterial gate tunnel field effect transistor with lateral energy band profile modulation [J].
Cui, Ning ;
Liang, Renrong ;
Xu, Jun .
APPLIED PHYSICS LETTERS, 2011, 98 (14)