Metal Wafer Bonding for 3D Interconnects and Advanced Packaging

被引：0
|
作者：
Dragoi, V. [1 ]
Pabo, E. [2 ]
Wagenleitner, T. [1 ]
Floetgen, C. [1 ]
Rebhan, B. [1 ]
Corn, K. [2 ]
机构：
[1] EV Grp, DI E Thallner Str 1, A-4782 St Florian, Austria
[2] EV Grp Inc, Tempe, AZ 85284 USA
来源：
2012 13TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY & HIGH DENSITY PACKAGING (ICEPT-HDP 2012) | 2012年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Metal films can be used as bonding layers at wafer-level in manufacturing processes for device assembly as well as just for electrical integration of different components. One has to distinguish between two categories of processes: metal thermo-compression bonding on one side, and bonding with formation of a eutectic or an intermetallic alloy layer. The different process principles determine also the applications area for each. From electrical interconnections to wafer-level packaging (with special emphasis on vacuum packaging) metal wafer bonding is a very important technology in manufacturing processes.
引用
收藏
页码：114 / 120
页数：7
相关论文
共 50 条
  • [1] Wafer level interconnects for 3D packaging
    Banerjee, SR
    Drayton, RF
    54TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, VOLS 1 AND 2, PROCEEDINGS, 2004, : 1513 - 1518
  • [2] Wafer-level 3D interconnects via Cu bonding
    Morrow, P
    Kobrinsky, MJ
    Ramanathan, S
    Park, CM
    Harmes, M
    Ramachandrarao, V
    Park, HM
    Kloster, G
    List, S
    Kim, S
    ADVANCED METALLIZATION CONFERENCE 2004 (AMC 2004), 2004, : 125 - 130
  • [3] Enabling Die-to-Wafer Hybrid Bonding for the Next Generation Advanced 3D Packaging
    Hung, Raymond
    See, Gilbert
    Wang, Ying
    Yong, Chang Bum
    Zheng, Ke
    Chang, Yauloong
    Shantaram, Avi
    Wang, Ruiping
    Sundarrajan, Arvind
    Abdilla, Jonathan
    Hegde, Nithyananda
    Schmid, Stefan
    Bikaljevic, Djuro
    Glantschnig, Manfred
    PROCEEDINGS OF THE IEEE 74TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, ECTC 2024, 2024, : 778 - 783
  • [4] Enabling 3D Interconnects with Metal Direct Bonding
    Di Cioccio, Lea
    Gueguen, Pierric
    Signamarcheix, Thomas
    Rivoire, Maurice
    Scevola, D.
    Cahours, Regis
    Leduc, Patrick
    Assous, M.
    Clavelier, Laurent
    PROCEEDINGS OF THE 2009 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2009, : 152 - +
  • [5] Modelling and characterization on wafer to wafer hybrid bonding technology for 3D IC packaging
    Ji, L.
    Che, F. X.
    Ji, H. M.
    Li, H. Y.
    Kawano, M.
    2019 IEEE 21ST ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC), 2019, : 87 - 94
  • [6] Through wafer interconnects for 3-D packaging
    Moll, Amy J.
    Knowlton, William B.
    Oxford, Rex
    ENABLING TECHNOLOGIES FOR 3-D INTEGRATION, 2007, 970 : 163 - +
  • [7] Polymer Direct Bonding Characterization in Wafer Level Packaging for 3D Integration
    Ou-Yang, T. Y.
    Hsiao, C. C.
    Lee, O. H.
    Chiang, C. W.
    Fu, H. C.
    Lin, W. H.
    Chang, H. H.
    2021 16TH INTERNATIONAL MICROSYSTEMS, PACKAGING, ASSEMBLY AND CIRCUITS TECHNOLOGY CONFERENCE (IMPACT), 2021, : 173 - 176
  • [8] 3D wafer level packaging
    Savastiouk, S
    Siniaguine, O
    Korczynski, E
    Tilenschi, M
    MICRO MATERIALS, PROCEEDINGS, 2000, : 240 - 243
  • [9] 3D wafer level packaging
    Savastiouk, S
    Siniaguine, O
    Korczynski, E
    2000 HD INTERNATIONAL CONFERENCE ON HIGH-DENSITY INTERCONNECT AND SYSTEMS PACKAGING, 2000, 4217 : 26 - 31
  • [10] Advanced techniques for 3D devices in wafer-bonding processes
    Lindner, P
    Dragoi, V
    Farrens, S
    Glinsner, T
    Hangweier, P
    SOLID STATE TECHNOLOGY, 2004, 47 (06) : 55 - +
12345