Multi-Object Tracking Coprocessor for Multi-Channel Embedded DVR Systems

In this paper, the architecture of a video analytics coprocessor is proposed for multi-channel embedded digital video recorder (DVR) systems. A reference video analytics algorithm is proposed for multi-object tracking and is divided into independent processing steps based on data flow. Each step is designed in hardware or software considering its computational complexity and required system resources. Pixel-wise processing requiring a large amount of computational resources, such as frame difference and background modeling, are designed as hardware with embedded direct memory access (DMA) controllers. A single-pass connected component labeling (CCL) is designed as a hardware targeting real-time processing of stream input. High-level tasks such as object filtering, frame-based control of hardware modules, and communication with an external host are designed with software on an embedded processor. Object tracking and event detection are designed with software on a host processor. Considering both the bandwidth required for frame processing and the bandwidth available by memory buses, the architecture of a 4-channel video analytics coprocessor is explored. It is finally implemented on a field-programmable gate arrays (FPGA) device, integrated into a conventional DVR system, and verified as to its functions and performance. It can provide video analysis functions to conventional DVR system-on-chip (SoC), and can lessen the cost of real-time video monitoring at remote monitoring centers(1).