Characterization of Nanowire CMOS Amplifiers Using Fully Depleted Surrounding Gate Transistors

Vertical nanowire SGFETs (Surrounding Gate Field Effect Transistors) provide full gate control over the channel to eliminate short channel effects and achieve extremely low OFF current. This paper presents the fully depleted BSIMSOI modeling of low power NMOS and PMOS SGFETs with 10 nm channel length and 2 nm channel radius, extraction of distributed device parasitics and potential applications of these transistors for high speed analog circuits. When biased with V(ds) = 0.5 V and V(gs) = 0.5 V at the active operating region, NMOS and PMOS SGFETs have 2 mu A and 0.7 mu A drain currents, 14 mu A/V and 8 mu A/V transconductances, 400 k Omega and 1.1 M Omega output resistances, 36 THz and 25 THz unity current gain cutoff frequencies and 120 THz and 100 THz maximum frequency of oscillations, respectively. The differential-pair amplifier realized with SGFETs dissipates 5 A,W power and provides 5 THz bandwidth with a voltage gain of 16, a linear output voltage swing of 0.5 V and a distortion better than 3% from a 1.8 V power supply and a 20 aF capacitive load. The 2nd and 3rd order harmonic distortions of the amplifier are -40 dBm and -52 dBm, respectively, and the 3rd order intermodulation is -24 dBm for a two-tone input signal with 10 mV amplitude and 10 GHz frequency spacing. All these parameters indicate that vertical nanowire surrounding gate transistors are promising candidates for the next generation VLSI technology.