A 6-Gb/s Differential Voltage Mode Driver with Independent Control of Output Impedance and Pre-Emphasis Level

被引：2

作者：

Bae, Chang-Hyun ^{[1
,2
]}

Choi, Dong-Ho ^{[1
]}

Ahn, Keun-Seon ^{[1
]}

Yoo, Changsik ^{[1
]}

机构：

[1] Hanyang Univ, Integrated Circuits Lab, Seoul 133791, South Korea

[2] Samsung Elect, DRAM Design Dept, Hwasung, South Korea

来源：

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | 2013年 / 13卷 / 05期

关键词：

Voltage-Mode driver; impedance calibration; pre-emphasis; CMOS; EQUALIZATION; TRANSMITTER; CMOS;

D O I：

10.5573/JSTS.2013.13.5.423

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 6-Gb/s differential voltage mode driver is presented whose output impedance and pre-emphasis level can be controlled independently. The voltage mode driver consists of five binary-weighted slices each of which has four sub-drivers. The output impedance is controlled by the number of enabled slices while the pre-emphasis level is determined by how many sub-drivers in the enabled slices are driven by post-cursor input. A prototype transmitter with a voltage-mode driver implemented in a 65-nm CMOS logic process consumes 34.8-mW from a 1.2-V power supply and its pre-emphasized output signal shows 165-mVpp,diff and 0.56-UI eye opening at the end of a cable with 10-dB loss at 3-GHz.

引用

页码：423 / 429

页数：7

共 12 条

[1]

[Anonymous], IEEE INT C MICR CAIR

[2]

Green MM, 2003, PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, P204

[3] A 10-mW 3.6-Gbps I/O transmitter [J].

Hatamkhani, H ;

Wong, KLJ ;

Drost, R ;

Yang, CKK .

2003 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2003, :97-98

[4]

Jin Liu, 2004, IEEE Circuits and Systems Magazine, V4, P4, DOI 10.1109/MCAS.2004.1330746

[5] A T-Coil-Enhanced 8.5 Gb/s High-Swing SST Transmitter in 65 nm Bulk CMOS With <-16 dB Return Loss Over 10 GHz Bandwidth [J].

Kossel, Marcel ;

Menolfi, Christian ;

Weiss, Jonas ;

Buchmann, Peter ;

von Bueren, George ;

Rodoni, Lucio ;

Morf, Thomas ;

Toifl, Thomas ;

Schmatz, Martin .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2008, 43 (12) :2905-2920

[6] A multigigabit backplane transceiver core in 0.13-μm CMOS with a power-efficient equalization architecture [J].

Krishna, K ;

Yokoyama-Martin, DA ;

Caffee, A ;

Jones, C ;

Loikkanen, M ;

Parker, J ;

Segelken, R ;

Sonntag, JL ;

Stonick, J ;

Titus, S ;

Weinlader, D ;

Wolfer, S .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40 (12) :2658-2666

[7]

Menolfi C., 2007, IEEE International Solid-State Circuits Conference, P446

[8] A 20Gb/s SerDes Transmitter with Adjustable Source Impedance and 4-tap Feed-Forward Equalization in 65nm Bulk CMOS [J].

Philpott, R. A. ;

Humble, J. S. ;

Kertis, R. A. ;

Fritz, K. E. ;

Gilbert, B. K. ;

Daniel, E. S. .

PROCEEDINGS OF THE IEEE 2008 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2008, :623-626

[9]

Song J.-H., 2010, INT TECH C CIRC SYST

[10] A 27-mW 3.6-Gb/s I/O transceiver [J].

Wong, KLJ ;

Hatamkhani, H ;

Mansuri, M ;

Yang, CKK .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (04) :602-612

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