Minimum energy solution for ultra-low power applications

被引：2

作者：

Guduri, M. ^{[1
]}

Dokania, V. ^{[1
]}

Verma, R. ^{[1
]}

Islam, A. ^{[1
]}

机构：

[1] BIT, Dept ECE, Ranchi 835215, Jharkhand, India

来源：

MICROSYSTEM TECHNOLOGIES-MICRO-AND NANOSYSTEMS-INFORMATION STORAGE AND PROCESSING SYSTEMS | 2019年 / 25卷 / 05期

关键词：

OPERATION;

D O I：

10.1007/s00542-018-3785-6

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper examines device sizing of CMOS inverter circuit at 22-nm technology node using predictive technology model in deep subthreshold region. Channel length (L) of the device is resolved to obtain optimized threshold voltage @ supply voltage of 150mV. Aspect ratio of Inverter logic gate is determined for the same supply voltage. Symmetrical transient response analysis is performed. It is found that the inverter logic gate is symmetric when aspect ratio () is equal to 3.71. Minimum propagation delay is found and observed that high performance circuit design is achievable for higher ratios. At L=66nm, optimum threshold voltage is obtained. Minimum energy point is also obtained at ratio of 3.71 at 122mV.

引用

页码：1823 / 1831

页数：9

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