A Memory-Efficient High-Throughput Architecture for Lifting-Based Multi-Level 2-D DWT

被引:29
|
作者
Hu, Yusong [1 ]
Jong, Ching Chuen [2 ]
机构
[1] Nanyang Technol Univ, Integrated Syst Res Lab, Sch Elect & Elect Engn, Singapore 639798, Singapore
[2] Nanyang Technol Univ, Sch Elect & Elect Engn, Singapore 639798, Singapore
关键词
Discrete wavelet transform (DWT); lifting-scheme; scalable parallel multi-level 2-D DWT; stripe-based scanning method; DISCRETE WAVELET TRANSFORM; VLSI ARCHITECTURE; HIGH-PERFORMANCE; 1-D;
D O I
10.1109/TSP.2013.2274640
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, we present a novel memory-efficient high-throughput scalable architecture for multi-level 2-D DWT. We studied the existing DWT architectures and observed that data scanning method has a significant impact on the memory efficiency of DWT architecture. We propose a novel parallel stripe-based scanning method based on the analysis of the dependency graph of the lifting scheme. With the new scanning method for multi-level 2D DWT, a high memory efficient scalable parallel pipelined architecture is developed. The proposed architecture requires no frame memory and a temporal memory of size only for the 3-level DWT decomposition with an image of size pixels with 32 pixels processed concurrently. The elimination of frame memory and the small temporal memory lead to significant reduction in overall size. The proposed architecture has a regular structure and achieves 100% hardware utilization. The synthesis results in 90 nm CMOS process show that the proposed architecture achieves a better area-delay product by 60% and higher throughput by 97% when compared to the best existing design for the CDF (Cohen-Daubechies-Favreau) 9/7 2-D DWT.
引用
收藏
页码:4975 / 4987
页数:13
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