FPGA-based real-time Phase Measuring Profilometry algorithm design and implementation

被引：2

作者：

Zhan, Guomin ^{[1
]}

Tang, Hongwei ^{[1
]}

Zhong, Kai ^{[1
]}

Li, Zhongwei ^{[1
]}

Shi, Yusheng ^{[1
]}

机构：

[1] Huazhong Univ Sci & Technol, State Key Lab Mat Proc & Die & Mould Technol, Wuhan 430074, Peoples R China

来源：

OPTICAL METROLOGY AND INSPECTION FOR INDUSTRIAL APPLICATIONS IV | 2016年 / 10023卷

基金：

美国国家科学基金会; 中国博士后科学基金;

关键词：

FPGA; Phase measuring profilometry; Multi-frequency heterodyne principle; Pipeline;

D O I：

10.1117/12.2245375

中图分类号：

O43 [光学];

学科分类号：

070207 ; 0803 ;

摘要：

Phase measuring profilometry (PMP) has been widely used in many fields, like Computer Aided Verification (CAV), Flexible Manufacturing System (FMS) et al. High frame-rate (HFR) real-time vision-based feedback control will be a common demands in near future. However, the instruction time delay in the computer caused by numerous repetitive operations greatly limit the efficiency of data processing. FPGA has the advantages of pipeline architecture and parallel execution, and it fit for handling PMP algorithm. In this paper, we design a fully pipelined hardware architecture for PMP. The functions of hardware architecture includes rectification, phase calculation, phase shifting, and stereo matching. The experiment verified the performance of this method, and the factors that may influence the computation accuracy was analyzed.

引用

页数：11

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