PERFORMANCE ANALYSIS OF VLSI ARCHITECTURE OF VITERBI DECODER IN WLAN USING THE SLEEPY KEEPER TECHNIQUE

Rapid developments in the field of wireless communication have created a rising demand for Viterbi decoder with long battery life, low power dissipation, and low weight. There is a necessity in high data bandwidth continuing to drive communications systems in convolutional coding for error control. In this paper, two techniques are incorporated to address the issues. The first is by including the circuit level design of the architecture of the Viterbi decoder using a sleepy keeper technique, which reduces the leakage power dissipation. The second method is by proposing the modified register exchange algorithm, which reduces the occurrence of error probability with low power in signal transmission in the wireless domain. The simulation of the design at the transistor level is carried out in T-SPICE with 45 nm TSMC. The results of the simulation specify that the proposed method improves the overall performance in terms of low power, high speed, and signal to noise ratio or BER which is used in WLAN application.