A COMPACT FPGA-BASED SINGLE-PHASE CASCADED H-BRIDGE MULTILEVEL INVERTER FOR TEACHING AND RESEARCH ACTIVITIES

In this paper is presented the implementation of a compact FPGA-based single-phase cascaded H-bridge multilevel inverter suitable for teaching and research activities. The softwares Matlab/Simulink and Quartus II were used to describe and simulate the PWM algorithm in hardware description language (VHDL), before experimental implementation. A Terasic DE0-Nano board with an Intel Cyclone IV EP4CE22F17C6N FPGA was used to generate the 2.4 kHz PWM switching control signals, which are fed to isolated gate drivers with the HCPL-3180 optocoupler, before being applied to the eight IRF640N MOSFETs in a developed low power prototype inverter board. To validate the proposed inverter, two amplitude modulation indexes were evaluated (0.4 and 0.99) using the phase opposition carriers disposition (POD) technique. Simulation and experimental results to synthesize a three- and a five-level PWM voltage waveform across a resistive and a resistive-inductive capacitive load show that both are in close agreement, validating the proposed low-cost inverter.