An IR-Drop Aware Test Pattern Generator for Scan-Based At-Speed Testing

被引：1

作者：

Hou, Po-Fan ^{[1
]}

Lin, Yi-Tsung ^{[1
]}

Huang, Jiun-Lang ^{[1
]}

Shih, Ann ^{[2
]}

Conroy, Zoe F. ^{[2
]}

机构：

[1] Natl Taiwan Univ, Grad Inst Elect Engn, Dept Elect Engn, Taipei 106, Taiwan

[2] Cisco Syst Inc, Boxboro, MA USA

来源：

2016 IEEE 25TH ASIAN TEST SYMPOSIUM (ATS) | 2016年

关键词：

full scan; at-speed testing; yield loss; IR-drop; test power management; maximum-implication random-fill;

D O I：

10.1109/ATS.2016.23

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The excessive circuit switching activity during scan-based at-speed testing has been known to cause yield loss because it degrades the circuit performance and can cause a good device to fail the test. In this paper, we propose an IR-drop aware test pattern generator to produce high-quality at-speed test patterns. The idea is to manage the switching activity distribution of the generated test patterns so that the resulting IR-drop profiles match the user-specified ones. To improve the efficiency of the IR-drop matching process, the maximum-implication random-fill (MIR-fill) based IR-drop matching technique is developed. Simulation results show that the proposed test pattern generator achieves 20 times speedup compared to the previous work and also delivers significant IR-drop cost reduction.

引用

页码：167 / 172

页数：6

共 17 条

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Li, Yi-Hua
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Hsieh, Wen-Wen
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Hwang, TingTing
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2010, 29 (02) : 289 - 298
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Tsai, Ming-Hong
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Hsieh, Hung-Yi
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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2014, 22 (09) : 1980 - 1989
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Lin, Yi-Tsung
Huang, Jiun-Lang
Wen, Xiaoqing
2011 IEEE INTERNATIONAL TEST CONFERENCE (ITC), 2011,
[6] Test Pattern Modification for Average IR-Drop Reduction
Ding, Wei-Sheng
Hsieh, Hung-Yi
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Li, James Chien-Mo
Wen, Xiaoqing
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 24 (01) : 38 - 49
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Tomita, Akihiro
Wen, Xiaoqing
Sato, Yasuo
Kajihara, Seiji
Miyase, Kohei
Holst, Stefan
Girard, Patrick
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IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2014, E97D (10): : 2706 - 2718
[8] Test compaction for at-speed testing of scan circuits based on nonscan test sequences and removal of transfer sequences
Pomeranz, I
Reddy, SM
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2002, 21 (06) : 706 - 714
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Li, Fuqiang
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Miyase, Kohei
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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2016, E99A (12) : 2310 - 2319
[10] PHS-Fill: A Low Power Supply Noise Test Pattern Generation Technique for At-Speed Scan Testing in Huffman Coding Test Compression Environment
Lin, Yi-Tsung
Wu, Meng-Fan
Huang, Jiun-Lang
PROCEEDINGS OF THE 17TH ASIAN TEST SYMPOSIUM, 2008, : 391 - 396

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