Heterogeneous Wafer reconstruction and wafer level hybridization by Copper Direct Bonding for Infrared imagers

被引:0
作者
Mani, Abdenacer Ait [1 ]
Huet, Stephanie [1 ]
机构
[1] LETI, CEA, F-38054 Grenoble 9, France
来源
2013 EUROPEAN MICROELECTRONICS PACKAGING CONFERENCE (EMPC) | 2013年
关键词
CMP (Chemical and Mechanical Polishing); Grinding; PECVD (Plasma Enhanced Chemical Vapor Deposition); Heterogeneous wafers; reconstructed wafers; CTE(Coefficient of Thermal Expansion); ECD (Electro Chemical Deposition); Direct Bonding;
D O I
暂无
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
The manufacturing technology of Infrared imagers suffers since the beginning of a lack of competitiveness compared to the Silicon based manufacturing technologies (wafer sizes, yield, volumes produced.). A special care is needed for the manipulation of wafers which are more fragile than Silicon due to their metallurgical composition. The mass, greater than Silicon act often as a limitation factor when a quick automatic manipulation is needed. The study we have undertaken and described in this paper shows that it is possible to reduce the gap between the IR and the Silicon Fields by processing directly a III-V substrate on a standard Silicon production line (200 or 300 mm). The obtained results are very encouraging for a so initial big challenge. In order to do that, it is necessary to build a heterogeneous wafer so that the assembly can act as a transparent new wafer for all the operations of Oxide deposition, metals deposition, photolithography, etching, CMP, cleaning, direct bonding with alignment procedure, thermal annealing, Grinding, Polishing, Final dicing and test. Finally, one of the most difficult parameter to conform to our need was the process temperatures, we lead in that way a manufacturing process flow respecting the maximum temperature which does not degrade the integrity of potential photodiodes present onto the InSb substrate. From the first transfer of the InSb substrate on the Silicon Host until the final annealing of the direct bonding assembly, all the operations were done along a temperature process flow under 300 degrees C.
引用
收藏
页数:8
相关论文
共 30 条
  • [1] Wafer Level Metallic Bonding: Voiding Mechanisms Copper Layers
    Imbert, B.
    Gondcharton, P.
    Benaissa, L.
    Fournel, F.
    Verdier, M.
    2015 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE AND 2015 IEEE MATERIALS FOR ADVANCED METALLIZATION CONFERENCE (IITC/MAM), 2015, : 201 - 203
  • [2] Low Temperature Direct Bonding for Hermetic Wafer level Packaging
    Nie, Lei
    Shi, Tielin
    Tang, Zirong
    Liu, Shiyuan
    Liao, Guanglan
    2009 4TH IEEE INTERNATIONAL CONFERENCE ON NANO/MICRO ENGINEERED AND MOLECULAR SYSTEMS, VOLS 1 AND 2, 2009, : 472 - 475
  • [3] Radius of curvature considerations for direct wafer bonding
    Hong, LN
    Bower, RW
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 1998, 37 (11): : 5932 - 5936
  • [4] Direct bonding with on-wafer metal interconnections
    C. Jia
    M. Wiemer
    T. Gessner
    Microsystem Technologies, 2006, 12 : 391 - 396
  • [5] Effect of nanotopography in direct wafer bonding: Modeling and measurements
    Turner, KT
    Spearing, SM
    Baylies, WA
    Robinson, M
    Smythe, R
    IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 2005, 18 (02) : 289 - 296
  • [6] Application of Wafer Direct Bonding Technique to Optical Nonreciprocal Devices
    Mizumoto, Tetsuya
    Takei, Ryohei
    IEEE PHOTONICS JOURNAL, 2011, 3 (03): : 588 - 596
  • [7] Wafer bonding process for zero level vacuum packaging of MEMS
    Sordo, Guido
    Collini, Cristian
    Moe, Sigurd
    Poppe, Erik
    Wright, Daniel Nilsen
    2020 IEEE 8TH ELECTRONICS SYSTEM-INTEGRATION TECHNOLOGY CONFERENCE (ESTC), 2020,
  • [8] Low Temperature Hydrophilic SiC Wafer Level Direct Bonding for Ultrahigh-Voltage Device Applications
    Zhang, Wenting
    Zhang, Caorui
    Wu, Junmin
    Yang, Fei
    An, Yunlai
    Hu, Fangjing
    Fan, Ji
    MICROMACHINES, 2021, 12 (12)
  • [9] High Precision Direct Transfer Bonding for Submicron Die-to-wafer in 3D/Heterogeneous Integration
    Sano, Ichiro
    Yamada, Katsuya
    Hirai, Yuya
    Yamagishi, Masanori
    Takyu, Shinya
    Fumita, Yusuke
    Kurita, Yoichiro
    2024 IEEE 10TH ELECTRONICS SYSTEM-INTEGRATION TECHNOLOGY CONFERENCE, ESTC 2024, 2024,
  • [10] TEOS and thermal oxide low temperature direct wafer bonding dynamics
    Michaud, L. G.
    Abadie, K.
    Fournel, F.
    Morales, C.
    Larrey, V.
    Caulfield, B.
    Wimplinger, M.
    JAPANESE JOURNAL OF APPLIED PHYSICS, 2025, 64 (04)