Computational Modeling of Hot-Spot Identification and Control in 3-D Stacked Chips with Integrated Cooling

被引：13

作者：

Alfieri, Fabio ^{[1
]}

Gianini, Sacha ^{[1
]}

Tiwari, Manish K. ^{[1
]}

Brunschwiler, Thomas ^{[2
]}

Michel, Bruno ^{[2
]}

Poulikakos, Dimos ^{[1
]}

机构：

[1] ETH, Dept Mech & Proc Engn, Lab Thermodynam Emerging Technol, CH-8092 Zurich, Switzerland

[2] IBM Zurich Res Lab, Ruschlikon, Switzerland

来源：

NUMERICAL HEAT TRANSFER PART A-APPLICATIONS | 2014年 / 65卷 / 03期

关键词：

HEAT-TRANSFER ENHANCEMENT; PIN-FIN; PRESSURE-DROP; FLOW; SINK; PERFORMANCE; CONVECTION; CHANNELS; ARRAYS;

D O I：

10.1080/10920277.2013.826480

中图分类号：

O414.1 [热力学];

学科分类号：

摘要：

In 3-D chip stacks, the electronic design may lead to a variety of different hot-spot scenarios and through-silicon-via (TSV) arrangements and distributions. In the present work, the influence and implications of the integrated water-cooling, TSV distribution, and size on the control of inhomogeneous hot-spots in such stacks is investigated. The numerical model consists of a row of 50 inline cylindrical micropin fins (of different size) inside a microcavity. Material properties are modeled as temperature-dependent, and the Reynolds number ranges from 60 to 180. An optimal design of hot-spots arrangements and TSV sizes is found to reduce the maximal temperature in the chip by up to 20%, and increase the average heat transfer by up to 30%.

引用

页码：201 / 215

页数：15

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