On the scalability of source/drain current enhancement in thin film sSOI

被引：20

作者：

Augendre, E ^{[1
]}

Eneman, G ^{[1
]}

De Keersgieter, A ^{[1
]}

Simons, V ^{[1
]}

De Wolf, I ^{[1
]}

Ramos, J ^{[1
]}

Brus, S ^{[1
]}

Pawlak, B ^{[1
]}

Severi, S ^{[1
]}

Leys, F ^{[1
]}

Sleeckx, E ^{[1
]}

Locorotondo, S ^{[1
]}

Ercken, M ^{[1
]}

de Marneffe, JF ^{[1
]}

Fei, L ^{[1
]}

Seacrist, M ^{[1
]}

Kellerman, B ^{[1
]}

Goodwin, M ^{[1
]}

De Meyer, K ^{[1
]}

Jurczak, M ^{[1
]}

Biesemans, S ^{[1
]}

机构：

[1] Interuniv Microelect Ctr, IMEC, B-3001 Louvain, Belgium

来源：

PROCEEDINGS OF ESSDERC 2005: 35TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | 2005年

关键词：

D O I：

10.1109/ESSDER.2005.1546645

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper demonstrates for the first time the scalability of source/drain current enhancement on low-doped thin film strained silicon on insulator (sSOI) substrate. Current improvement is maintained in narrow channel NFETs despite the relaxation from biaxial to uniaxial tensile strain after mesa patterning. Using strained contact etch-stop layers (sCESL), additional boost is achieved in short devices, resulting in 50% improvement in the drive current of 50 nm gate length devices with respect to conventional reference SOI process.

引用

页码：301 / 304

页数：4