CC-RTSV: Cross-Cellular Based Redundant TSV Design for 3D ICs

被引:1
作者
Ni, Tianming [1 ]
Shu, Yue [2 ]
Chang, Hao [3 ]
Lu, Lin [1 ]
Dai, Guangzhen [1 ]
Zhu, Shidong [1 ]
Qu, Chengming [1 ]
Huang, Zhengfeng [3 ]
机构
[1] Anhui Polytech Univ, Key Lab Adv Percept & Intelligent Control High En, Coll Elect Engn, Minist Educ, Wuhu 241000, Anhui, Peoples R China
[2] Hefei Univ Technol, Sch Elect Sci & Appl Phys, Hefei 230009, Anhui, Peoples R China
[3] Anhui Univ Finance & Econ, Dept Comp Sci & Technol, Bengbu 233030, Anhui, Peoples R China
关键词
3D-ICs; TSVs; redundancy; yield; THROUGH-SILICON; REPAIR;
D O I
10.1142/S0218126620501443
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Due to the winding level of the thinned wafers and the surface roughness of silicon dies, the quality of through-silicon vias (TSVs) varies during the fabrication and bonding process. If one TSV exhibits a defect during its manufacturing process, the probability of multiple defects occurring in the TSVs neighboring increases the faulty TSVs (FTSV), i.e., the TSV defects tend to be clustered which significantly reduces the yield of three-dimensional integrated circuits (3D-ICs). To resolve the clustered TSV faults, router-based and ring-based redundant TSV (RTSV) architecture were proposed. However, the repair rate is low and the hardware overhead is high. In this paper, we propose a novel cross-cellular based RTSV architecture to utilize the area more efficiently as well as to maintain high yield. The simulation results show that the proposed architecture has higher repair rate as well as more cost-effective overhead, compared with router-based and ring-based methods.
引用
收藏
页数:19
相关论文
共 19 条
[1]   A survey of optimization techniques for thermal-aware 3D processors [J].
Cao, Kun ;
Zhou, Junlong ;
Wei, Tongquan ;
Chen, Mingsong ;
Hu, Shiyan ;
Li, Keqin .
JOURNAL OF SYSTEMS ARCHITECTURE, 2019, 97 :397-415
[2]   Novel Spare TSV Deployment for 3-D ICs Considering Yield and Timing Constraints [J].
Chen, Yu-Guang ;
Wen, Wan-Yu ;
Shi, Yiyu ;
Hon, Wing-Kai ;
Chang, Shih-Chieh .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2015, 34 (04) :577-588
[3]   TSV Redundancy: Architecture and Design Issues in 3-D IC [J].
Hsieh, Ang-Chih ;
Hwang, TingTing .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2012, 20 (04) :711-722
[4]  
Jiang L, 2012, DES AUT TEST EUROPE, P793
[5]   On Effective Through-Silicon Via Repair for 3-D-Stacked ICs [J].
Jiang, Li ;
Xu, Qiang ;
Eklow, Bill .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2013, 32 (04) :559-571
[6]   8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology [J].
Kang, Uksong ;
Chung, Hoe-Ju ;
Heo, Seongmoo ;
Park, Duk-Ha ;
Lee, Hoon ;
Kim, Jin Ho ;
Ahn, Soon-Hong ;
Cha, Soo-Ho ;
Ahn, Jaesung ;
Kwon, DukMin ;
Lee, Jae-Wook ;
Joo, Han-Sung ;
Kim, Woo-Seop ;
Jang, Dong Hyeon ;
Kim, Nam Seog ;
Choi, Jung-Hwan ;
Chung, Tae-Gyeong ;
Yoo, Jei-Hwan ;
Choi, Joo Sun ;
Kim, Changhyun ;
Jun, Young-Hyun .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2010, 45 (01) :111-119
[7]   Minimal Buffer Insertion Based Low Power Clock Tree Synthesis for 3D Integrated Circuits [J].
Kumar, Kamineni Sumanth ;
Reuben, John .
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2016, 25 (11)
[8]  
Lo W.-H., 2012, IEEE T VERY LARGE SC, V24, P3437
[9]  
Lo WH, 2015, DES AUT TEST EUROPE, P848
[10]  
Loi Igor, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), P598, DOI 10.1109/ICCAD.2008.4681638