A 1.2V CMOS multiplier for 10 Gbit/s equalization

被引：2

作者：

Abbott, J ^{[1
]}

Plett, C ^{[1
]}

Rogers, JWM ^{[1
]}

机构：

[1] Carleton Univ, Dept Elect, Ottawa, ON K1S 5B6, Canada

来源：

ESSCIRC 2005: PROCEEDINGS OF THE 31ST EUROPEAN SOLID-STATE CIRCUITS CONFERENCE | 2005年

关键词：

D O I：

10.1109/ESSCIR.2005.1541639

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes the design of a low power 1.2V CMOS multiplier for a 10 Gbit/s continuous time FIR filter. The multiplier can be digitally controlled without the use of a Digital to Analog Converter and has 32 possible gain settings from -1 to +1. To achieve negative gain an inverting switch is used at the input of the multiplier, reducing loading at the summing node by 50%. As the bandwidth bottle neck occurs at the summing node, this allows for higher frequency operation or an increase in the number of multipliers per summing node. The gain errors are less than 2%, linearity errors are less than 3.3%, and the power consumption is 1.5mW.

引用

页码：379 / 382

页数：4