Research on FPGA Chip of Software/Hardware Co-Design for Calculating Super-high-order Matrix

Calculating super-high-order matrix is widely used in science and engineering, but the slow speed is a hard problem for researchers. This paper proposed a method of calculating super-high-order matrix in FPGA chips based on software/hardware co-design (SHDE). This chip is designed on a million-gate scale FPGA, and its core architecture is a systolic array which consists of thousands of special arithmetic units and executes the matrix operations in parallel. Finally, it breaks through the bottlenecks of slow speed on the calculation of super-high-order matrix, and really achieves the purpose of software/hardware co-design. Simulation results demonstrate that calculating super-high-order matrix based on the chip could obtain high precision results in a short period of time.