Design Of Sample and Hold Merged With 2.5 Bit Multiplying Digital-to-Analog Converter

被引：0
|
作者：
Wang, Xiao-lei [1 ]
Liang, Chang [1 ]
Guan, Xian-zhong [1 ]
Deng, Hong-hui [1 ]
机构：
[1] Hefei Univ Technol, Inst VLSI Design, Hefei, Peoples R China
来源：
2012 5TH INTERNATIONAL CONGRESS ON IMAGE AND SIGNAL PROCESSING (CISP) | 2012年
关键词：
SMDAC; op-sharing; transconductance-controlled; ADC;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A design of a SHA merged with MDAC(SMDAC) which can be used in a 14 bit 80Msps pipelined analog-to-digital converter (ADC) is presented in this paper. A two-stage transconductance-controlled op-amp is used in the SMDAC to ensure the requirment of the resolution, speed and stability of the circuit when its feedback factor alternate between 1/2 and 1/4. Simulation by cadence based on Chartered 0.18 mu 1P5M CMOS process under 1.8V supply voltage shows 116dB loop gain, 1.05GHz unity gain bandwidth and 61 degrees phase margin in two different feedback factors of the op-amp. The output signal of the S/H phase and MDAC phase can be settled to 14bit and 12bit accuracy in 5ns, respectively.
引用
收藏
页码：1403 / 1406
页数：4
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