共 50 条
- [32] A Compact 3-Stage Pipelined Hardware Accelerator for Point Multiplication of Binary Elliptic Curves Over GF(2233) [J]. IEEE ACCESS, 2024, 12 : 162510 - 162521
- [34] Efficient Hardware Implementation of the LEDAcrypt Decoder [J]. IEEE ACCESS, 2021, 9 : 66223 - 66240
- [35] A Pipelined FPGA Implementation of an Encryption Algorithm based on Genetic Algorithm [J]. MACHINE INTELLIGENCE AND BIO-INSPIRED COMPUTATION: THEORY AND APPLICATIONS VII, 2013, 8751
- [36] Hardware Implementation of the Stone Metamorphic Cipher [J]. INTERNATIONAL JOURNAL OF COMPUTER SCIENCE AND NETWORK SECURITY, 2010, 10 (08): : 54 - 60
- [38] A Hardware-efficient Implementation of CLOC for On-Chip Authenticated Encryption [J]. 2018 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), 2018, : 311 - 315
- [39] Pipelined Implementation of Camellia Encryption Algorithm [J]. 2016 24TH TELECOMMUNICATIONS FORUM (TELFOR), 2016, : 312 - 315
- [40] An Efficient Implementation of a Fully Combinational Pipelined S-Box on FPGA [J]. 2016 CONFERENCE OF BASIC SCIENCES AND ENGINEERING STUDIES (SCGAC), 2016, : 57 - 63