共 50 条
- [21] A Parallel Yet Pipelined Architecture for Efficient Implementation of the Advanced Encryption Standard Algorithm on Reconfigurable Hardware International Journal of Parallel Programming, 2016, 44 : 1102 - 1117
- [22] A Unified and Pipelined Hardware Architecture for Implementing Intra Prediction in HEVC 2014 IEEE SOUTHWEST SYMPOSIUM ON IMAGE ANALYSIS AND INTERPRETATION (SSIAI 2014), 2014, : 29 - 32
- [23] Hardware Implementation of HS1-SIV E-BUSINESS AND TELECOMMUNICATIONS (ICETE 2016), 2017, 764 : 179 - 194
- [24] High Throughput, Pipelined Implementation of AES on FPGA IEEC 2009: FIRST INTERNATIONAL SYMPOSIUM ON INFORMATION ENGINEERING AND ELECTRONIC COMMERCE, PROCEEDINGS, 2009, : 542 - 545
- [25] Pipelined RISC Processor Design and FPGA Implementation INDUSTRIAL INSTRUMENTATION AND CONTROL SYSTEMS II, PTS 1-3, 2013, 336-338 : 1550 - 1553
- [27] Architecture design and hardware implementation of AES encryption algorithm 2020 5TH INTERNATIONAL CONFERENCE ON MECHANICAL, CONTROL AND COMPUTER ENGINEERING (ICMCCE 2020), 2020, : 1611 - 1614
- [28] Hardware/Software Codesign and Implementation for Secure NFC Applications 2015 23RD SIGNAL PROCESSING AND COMMUNICATIONS APPLICATIONS CONFERENCE (SIU), 2015, : 2392 - 2395
- [29] High Performance Hardware Implementation of AES Using Minimal Resources 2013 INTERNATIONAL CONFERENCE ON INTELLIGENT SYSTEMS AND SIGNAL PROCESSING (ISSP), 2013, : 338 - 343