Variability aware low leakage reliable SRAM cell design technique

被引：37

作者：

Islam, A. ^{[1
]}

Hasan, Mohd ^{[2
]}

机构：

[1] Deemed Univ, Birla Inst Technol, Dept ECE, Ranchi, Jharkhand, India

[2] Aligarh Muslim Univ, Dept Elect Engn, Aligarh, Uttar Pradesh, India

来源：

MICROELECTRONICS RELIABILITY | 2012年 / 52卷 / 06期

关键词：

CMOS; CIRCUITS; ROBUST;

D O I：

10.1016/j.microrel.2012.01.003

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a technique for designing a low power SRAM cell. The cell achieves low power dissipation due to its series connected drivers driven by bitlines and read buffers which offer stack effect. The paper investigates the impact of process, voltage, and temperature (PVT) variations on standby leakage and finds appreciable improvement in power dissipation. It also estimates read/write delay, read stability, write-ability, and compares the results with that of standard 6T SRAM cell. The comparative study based on Monte Carlo simulation exhibits appreciable improvement in leakage power dissipation and other design metrics at the expense of 84% area overhead. (C) 2012 Elsevier Ltd. All rights reserved.

引用

页码：1247 / 1252

页数：6

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