Efficient implementation of the CCSDS 122.0-B-1 compression standard on a space-qualified field programmable gate array

An efficient architecture of the Consultative Committee for Space Data Systems (CCSDS) issued standard CCSDS 122.0-B-1 image data compression is presented. The architecture is implemented on a space-qualified field programmable gate array (FPGA). The implementation can provide both lossless and lossy compression with a simple and efficient rate control mechanism. The achievable throughput depends on embedding into an application architecture and is typically higher than 100 Mbps. The implementation has been successfully used in two space projects. Due to the programmability of FPGAs, the design can be quickly adapted to fit the needs of different satellite projects, and to meet the requirement of high data volume and high-speed processing capability in many space missions. To the best of our knowledge, our implementation is the first flight FPGA implementation of CCSDS image data compression for an ESA mission. (C) 2013 Society of Photo-Optical Instrumentation Engineers (SPIE)