64Mbit virtual channel synchronous DRAM

被引：0

作者：

Matsui, Y ^{[1
]}

Sakakibara, K ^{[1
]}

Yamamoto, A ^{[1
]}

Shimada, K ^{[1
]}

Shinohara, I ^{[1
]}

Kinoshita, M ^{[1
]}

机构：

[1] NEC Corp Ltd, LSI Memory Div 1, Tokyo, Japan

来源：

NEC RESEARCH & DEVELOPMENT | 1999年 / 40卷 / 03期

关键词：

DRAM; synchronous; virtual channel memory;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We have developed 64Mbit virtual channel SDRAM as a solution for multi memory master systems. The virtual channel memory is the name of the architecture that includes multiple data register region between memory array and interface circuits. This paper describes the basic architecture of the virtual channel SDRAM, detailed data transfer technology, peripheral circuits and actual evaluation data, indicating excellent performance in terms of both speed and power.

引用

页码：282 / 286

页数：5

共 46 条

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