Modeling for Critical Design and Performance of Wafer Level Chip Scale Package

被引：0

作者：

Liu, Yong ^{[1
]}

Qian, Qiuxiao ^{[1
]}

Ring, Matt ^{[1
]}

Kim, Jihwan ^{[1
]}

Kinzer, Dan ^{[1
]}

机构：

[1] Fairchild Semicond Corp, Portland, ME 04106 USA

来源：

2012 IEEE 62ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC) | 2012年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Comprehensive finite element analysis (FEA) modeling is carried out to improve the performance of critical designs of wafer level chip scale package (WLCSP). First, a design with one layer redistribution layout (RDL) copper with etched pocket in the non-covered UBM area and one layer polyimide structure (1Cu1Pi design) is investigated. Different polyimide layouts, copper thicknesses, pocket parameters and non-covered UBM diameters are studied through finite element modeling. Then, a stacked metal design with the sputtered copper UBM stacked on the RDL copper layer, with one polyimide layer between them (2Cu1Pi) for the WLCSP is examined. Parameter study of different UBM diameters with the same solder volume and different UBM diameters with the same solder joint height is conducted by the simulation. Finally the correlation and comparison of the failure mechanism between the modeling and the test are presented and discussed.

引用

页码：1174 / 1182

页数：9

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