Formal Design, Co-Simulation and Validation of a Radar Signal Processing System

With the ever increasing complexity in safety-critical and performance-demanding application domains such as automotive and avionics, the costs of designing, producing and especially testing systems does not scale well for the next generation of applications. One example is the active electronically scanned array (AESA) antenna signal processing chain, which is currently out-of-reach from consumer products but rather part of a few exclusive hi-tech appliances. To cope with the associated complexity of such systems, we propose a design flow starting from a high-level formal modeling language which captures and exposes important design properties to enable their systematic exploitation for the purpose of simulation, analysis and synthesis towards cost-efficient implementations. We demonstrate the capabilities of this approach by providing a compact yet expressive description of the AESA signal processing chain, generate automatic test-cases to verify the conformity of model with design specifications, synthesize a part of it to VHDL and co-simulate the generated artifact to validate its correctness.