A High Speed Encoder for a 5GS/s 5 Bit Flash ADC

被引：0

作者：

Varghese, George Tom ^{[1
]}

Mahapatra, K. K. ^{[1
]}

机构：

[1] Natl Inst Technol, Dept Elect & Commun Engn, Rourkela, India

来源：

2012 THIRD INTERNATIONAL CONFERENCE ON COMPUTING COMMUNICATION & NETWORKING TECHNOLOGIES (ICCCNT) | 2012年

关键词：

Analog to digital converter; Flash ADC; Pseudo dynamic CMOS logic;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The present investigation proposes an efficient high speed encoding scheme intended for a 5GS/s 5 bit flash analog to digital converter. The designing of a thermometer code to binary code is one of the challenging issues in the design of a high speed flash ADC. An encoder circuit in this paper translates the thermometer code into the intermediate gray code to reduce the effects of bubble errors. To increase the speed of the encoder, the implementation of the encoder through pseudo dynamic CMOS logic is presented. The proposed encoder is designed using 90nm technology at 1.2V power supply using CADENCE tool. The simulation results shown for a sampling frequency of 5GHz and the average power dissipation of the encoder is 1.919mW.

引用

页数：5