A SiCOHBEOL interconnect technology for high density and high performance 65 nm CMOS applications

被引:0
作者
Angyal, M [1 ]
Gill, J [1 ]
Inohara, M [1 ]
Ng, MF [1 ]
Rhee, SH [1 ]
Lane, S [1 ]
Hichri, H [1 ]
Penny, C [1 ]
Melville, I [1 ]
Ramachandran, V [1 ]
Zhang, BC [1 ]
Siew, YK [1 ]
Zhang, F [1 ]
Park, KC [1 ]
Lee, KW [1 ]
Kaltalioglu, E [1 ]
Kim, SO [1 ]
Matusiewicz, G [1 ]
Lin, YH [1 ]
Urata, K [1 ]
Kumar, K [1 ]
Linville, J [1 ]
Minami, M [1 ]
Maynard, H [1 ]
Hoinkis, M [1 ]
Bolom, T [1 ]
Feustel, F [1 ]
Lam, KS [1 ]
Inoue, K [1 ]
Simon, A [1 ]
Smith, J [1 ]
Baker-O'Neal, B [1 ]
Economikos, L [1 ]
Ong, P [1 ]
Ishikawa, Y [1 ]
Naujok, M [1 ]
Sakamoto, A [1 ]
Ema, T [1 ]
Lembach, G [1 ]
Kelling, M [1 ]
Bailey, T [1 ]
Marrokey, S [1 ]
Li, WK [1 ]
Christiansen, C [1 ]
Li, BZ [1 ]
Lee, T [1 ]
Chen, F [1 ]
Chanda, K [1 ]
Filippi, R [1 ]
McLaughlin, PV [1 ]
机构
[1] IBM Semicond Res & Dev Ctr, IBM Microelect Div, Hopewell Jct, NY 12533 USA
来源
Advanced Metallization Conference 2005 (AMC 2005) | 2006年
关键词
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中图分类号
TF [冶金工业];
学科分类号
0806 ;
摘要
The development and qualification of a 300 mm SiCOH Back End of Line (BEOL) integration for 65 nm bulk and SOI semiconductor product applications is presented. A hierarchical BEOL architecture is employed which allows up to 10 levels of copper metallization with as many as 8 levels built in SiCOH (k similar to 3) interlevel dielectric. The interconnect architecture renders this BEOL technology suitable for both high performance microprocessors and high density Application Specific Integrated Circuits (ASICs). Key process integration challenges overcome during the course of qualification are presented. The impact of these process improvements on electrical yield, defect density, reliability, and performance are discussed.
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页码:39 / 46
页数:8
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