A 10-bit 10 MS/s SAR ADC with the Reduced Capacitance DAC

被引：0

作者：

Kuo, Hsuan-Lun ^{[1
]}

Lu, Chih-Wen ^{[1
]}

Lin, Shuw-Guann ^{[2
]}

Chang, Da-Chiang ^{[2
]}

机构：

[1] Natl Tsing Hua Univ, Dept Engn & Syst Sci, Hsinchu, Taiwan

[2] Natl Chip Implementat Ctr, Natl Appl Res Labs, 101 Sect 2,Kuang Fu Rd, Hsinchu 30013, Taiwan

来源：

2016 5TH INTERNATIONAL SYMPOSIUM ON NEXT-GENERATION ELECTRONICS (ISNE) | 2016年

关键词：

charge redistribution; capacitor; successive approximation register (SAR); analog-to-digital converter (ADC); digital-to-analog converter (DAC); 40-MS/S;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a 10-bit 10 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) in 180 nm technology. We propose a new structure of the charge redistribution digital-to-analog converter (DAC) for the SAR ADC to reduce the area cost and power consumption and to promote the bandwidth. This structure does not only reduce the area of capacitors array and the capacitance of the DAC, but also guarantee the process variation of capacitors.

引用

页数：2

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