A 5.5 VSOPA line driver in a standard 1.2 V 0.13 μm CMOS technology

被引：22

作者：

Semeels, B ^{[1
]}

Steyaert, M ^{[1
]}

Dehaene, W ^{[1
]}

机构：

[1] Katholieke Univ Leuven, ESAT, MICAS, B-3001 Louvain, Belgium

来源：

ESSCIRC 2005: PROCEEDINGS OF THE 31ST EUROPEAN SOLID-STATE CIRCUITS CONFERENCE | 2005年

关键词：

D O I：

10.1109/ESSCIR.2005.1541620

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this work a high voltage line driver, using a Self-Oscillating Power Amplifier (SOPA) in a digital 1.2 V 0.13 mu m CMOS technology is presented. A selfbiasing cascode topology allows the line driver to operate at 4.5 times the nominal supply voltage. Oxide breakdown and hot carrier degradation is minimized since the driver operates within the voltage limits imposed by the design rules of a mainstream CMOS technology. The realized prototype delivers a 35 MHz PWM square wave with a 4.6 V swing in a 7.1 Omega load with an efficiency of 62%. The chip achieves a Spurious Free Dynamic Range (SFDR) of 52 dB while driving a I MHz sine wave. A missing tone power ratio (MTPR) of 50 dB has been measured for a DMT signal up to 1.1 MHz with a crest factor of 14 dB.

引用

页码：303 / 306

页数：4