Efficient Synchronization for Distributed Embedded Multiprocessors

被引：4

作者：

Xiao, Hao ^{[1
]}

Wu, Ning ^{[1
]}

Ge, Fen ^{[1
]}

Isshiki, Tsuyoshi ^{[2
]}

Kunieda, Hiroaki ^{[2
]}

Xu, Jun ^{[3
]}

Wang, Yuangang ^{[3
]}

机构：

[1] Nanjing Univ Aeronaut & Astronaut, Coll Elect & Informat Engn, Nanjing 210016, Jiangsu, Peoples R China

[2] Tokyo Inst Technol, Dept Commun & Comp Engn, Tokyo 1528550, Japan

[3] Huawei Technol Co Ltd, Shannon Lab, Beijing 100095, Peoples R China

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2016年 / 24卷 / 02期

基金：

中国国家自然科学基金;

关键词：

Distributed architecture; embedded multiprocessor; message passing; synchronization; LOW-COST; ON-CHIP;

D O I：

10.1109/TVLSI.2015.2408345

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In multiprocessor systems, low-latency synchronization is extremely important to effectively exploit fine-grain data parallelism and improve overall performance. This brief presents an efficient synchronization for embedded distributed multiprocessors. The proposed solution works in a completely decentralized request-response manner via explicit message exchange among the processing elements. Scalable lock and barrier synchronization algorithms, which are derived from the inherent distributed characteristics of the underlying architecture, are proposed to enable fair, orderly, and contention-free synchronization. We implement the proposed synchronization model in a distributed 32-core architecture with a commercial cycle-accurate SystemC simulation platform. Experimental results that show our proposed approach achieves ultralow synchronization latency and almost ideal scalability when the core count scales.

引用

页码：779 / 783

页数：5

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